FRIDAY, AUGUST 24, 2007, 11 a.m., TI Auditorium (Directions)
MARK RODWELL
Professor and Director of the UCSB Nanofabrication Laboratory and the NSF Nanofabrication Infrastructure Network (NNIN),
Director of the SRC Nonclassical CMOS Research Center,
The University of California, Santa Barbara
III-V Bipolar and Field-Effect Transistors: Applications, Performance Limits, THz Scaling Roadmaps
ABSTRACT:We examine the high-frequency performance limits of InP-based transistors. In most semiconductor electron devices, signal currents are generated by modulating electron flow though depletion regions. The resulting displacement currents are removed via Ohmic contacts to doped semiconductor layers. Bandwidth is then limited by access resistance, and the capacitance, carrier transit time, and space-charge resistance of depletion layers. Bandwidths are increased by decreasing depletion-layer thicknesses, reducing junction areas, and reducing metal-semiconductor contact resistances. Consideration of these classic effects is imperative in the development of any proposed high-frequency electron device.
III-V bipolar transistor scaling laws, limits, and roadmaps will be developed. Contact resistances and thermal resistances are the critical limits to further improvements in bandwidth. With InP-based bipolar transistors at the 64 nm scaling generation, 1-1.5 THz simultaneous current-gain and power-gain cutoff frequencies, 400 GHz digital ICs, and 750 GHz medium-power amplifiers appear feasible. Ongoing IC design efforts at UCSB, in collaboration with Teledyne Scientific will be considered, including sub-mm-wave power amplifiers, mm-wave digital ICs, and ~50 GHz loop bandwidth feedback amplifiers for low-intermodulation amplification at ~2-5 GHz.
We are investigating III-V-channel MOSFETs as a replacement for silicon MOSFETs at scaling generations below 22 nm. We will develop simplified scaling laws and examine scaling limits. While III-V channels provide higher carrier motilities than silicon, the low electron effective mass seriously limits the achievable drive current and impairs vertical scaling to the levels required for a 22 nm gate length device. These effects, which may render III-V MOSFETs uncompetitive with Silicon at the 22 nm node, are also highly relevant to the design of future III-V HEMTs scaled to attain THz bandwidths.
BIO: Mark Rodwell (Ph.D. , Stanford, 1988) is Professor and Director of the UCSB Nanofabrication Laboratory, the NSF Nanofabrication Infrastructure Network (NNIN), and Director of the SRC Nonclassical CMOS Research Center at the University of California, Santa Barbara. He was at AT&T Bell Laboratories during 1982-1984. His research focuses on high bandwidth InP bipolar transistors, compound semiconductor field-effect-transistors for VLSI applications, and mm-wave integrated circuit design in both silicon VLSI and III-V processes. His work on GaAs Schottky-diode ICs for mm-wave instrumentation was awarded the 1997 IEEE Microwave Prize, and he was elected IEEE Fellow in 2003.
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